用于深度学习的FPGA架构及其在行星机器人中的应用
FPGA Architecture for Deep Learning and its application to Planetary Robotics
摘要：
行星漫游者和航天器上的自主控制系统受益于学习等认知能力，以便能够适应现场的意外情况。Q-学习是强化学习的一种形式，在解决某些学习问题上已经取得了很好的效果。然而，行星漫游车和航天器上的嵌入式系统很少实现学习算法，这是由于该领域面临的限制，如处理能力、芯片尺寸、收敛速度和由于需要辐射加固而导致的成本。这些挑战提出了对便携式、低功耗、面积有效的硬件加速器的迫切需要，以使学习算法实用的机载空间硬件。提出了一种基于人工神经网络（ANN）的Q学习算法的FPGA实现。该方法将神经网络软件中固有的大规模并行性与FPGA硬件的细粒度并行性相匹配，从而显著减少处理时间。火星科学实验室目前使用赛灵思空间级Virtex FPGA器件进行图像处理、烟火操作控制和避障。我们在Xilinx Virtex 7 FPGA上模拟和编程我们的架构。已经展示了单个神经元Q学习和更复杂的多层感知（MLP）Q学习加速器的架构实现。结果显示，与传统的Intel i5 2.3 GHz CPU相比，Virtex 7 FPGA的速度提高了43倍。最后，我们使用Xilinx的Symphony仿真器和编译器对所提出的架构进行了仿真，并对性能和功耗进行了评估。
英文摘要：
Autonomous control systems onboard planetary rovers and spacecraft benefit from having cognitive capabilities like learning so that they can adapt to unexpected situations in-situ. Q-learning is a form of reinforcement learning and it has been efficient in solving certain class of learning problems. However, embedded systems onboard planetary rovers and spacecraft rarely implement learning algorithms due to the constraints faced in the field, like processing power, chip size, convergence rate and costs due to the need for radiation hardening. These challenges present a compelling need for a portable, low-power, area efficient hardware accelerator to make learning algorithms practical onboard space hardware. This paper presents a FPGA implementation of Q-learning with Artificial Neural Networks (ANN). This method matches the massive parallelism inherent in neural network software with the fine-grain parallelism of an FPGA hardware thereby dramatically reducing processing time. Mars Science Laboratory currently uses Xilinx-Space-grade Virtex FPGA devices for image processing, pyrotechnic operation control and obstacle avoidance. We simulate and program our architecture on a Xilinx Virtex 7 FPGA. The architectural implementation for a single neuron Q-learning and a more complex Multilayer Perception (MLP) Q-learning accelerator has been demonstrated. The results show up to a 43-fold speed up by Virtex 7 FPGAs compared to a conventional Intel i5 2.3 GHz CPU. Finally, we simulate the proposed architecture using the Symphony simulator and compiler from Xilinx, and evaluate the performance and power consumption.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
