MorphoNoC：利用纳米光子学探索可配置混合NoC的设计空间
MorphoNoC: Exploring the Design Space of a Configurable Hybrid NoC using Nanophotonics
摘要：
随着特征尺寸的减小降低了计算的能量，片上通信的功率预算正在稳步上升。此外，内核数量的增加给片上网络（NoC）基础设施带来了巨大的性能负担。虽然NoC被设计为允许扩展到数百个核心的常规架构，但缺乏灵活的拓扑结构会导致更高的延迟、更低的吞吐量和增加的能源成本。在本文中，我们探索MorphoNoCs -可扩展的，可配置的，混合NoCs通过扩展可配置的纳米光子链接的常规电气网络获得。为了设计MorphoNoCs，我们首先对多写多读（MWMR）纳米光子学链路的设计空间进行了详细的研究。在确定最佳设计点后，我们讨论了在混合电子光子NoCs中部署它们的路由器架构。然后，我们研究探索在网络级的设计空间，通过改变波导长度和混合路由器的数量。这使我们能够进行能量-延迟权衡。对于我们的评估，我们采用了合成基准测试以及NAS并行基准测试套件的跟踪。我们的研究结果表明，MorphoNoCs可以在基础电子网络上实现高达3.0倍的延迟改进或高达1.37倍的能量改进。
英文摘要：
As diminishing feature sizes drive down the energy for computations, the power budget for on-chip communication is steadily rising. Furthermore, the increasing number of cores is placing a huge performance burden on the network-on-chip (NoC) infrastructure. While NoCs are designed as regular architectures that allow scaling to hundreds of cores, the lack of a flexible topology gives rise to higher latencies, lower throughput, and increased energy costs. In this paper, we explore MorphoNoCs - scalable, configurable, hybrid NoCs obtained by extending regular electrical networks with configurable nanophotonic links. In order to design MorphoNoCs, we first carry out a detailed study of the design space for Multi-Write Multi-Read (MWMR) nanophotonics links. After identifying optimum design points, we then discuss the router architecture for deploying them in hybrid electronic-photonic NoCs. We then study explore the design space at the network level, by varying the waveguide lengths and the number of hybrid routers. This affords us to carry out energy-latency trade-offs. For our evaluations, we adopt traces from synthetic benchmarks as well as the NAS Parallel Benchmark suite. Our results indicate that MorphoNoCs can achieve latency improvements of up to 3.0x or energy improvements of up to 1.37x over the base electronic network.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
