基于并行架构协同设计的Householder变换高效实现及其对QR分解的加速
Efficient Realization of Householder Transform through Algorithm-Architecture Co-design for Acceleration of QR Factorization
摘要：
我们通过算法-架构协同设计实现了基于Householder变换（HT）的QR分解的高效实现，在Gflops/watt方面，我们实现了比最先进的多核、通用图形处理单元（GPGPU）、现场可编程门阵列（FPGA）和ClearSpeed CSX 700高3- 90倍的性能提升。经典HT的理论和实验分析的机会，表现出更高程度的并行性，其中并行性被量化为在有向无环图（DAG）的变换的每一个级别的并行操作的数量。基于对经典HT的理论分析，发现了一个机会，重新安排经典HT中的计算，从而产生了改进的HT（MHT），其中MHT表现出比经典HT高1.33倍的并行性。在用于HT和MHT的现成多核和通用图形处理单元（GPGPU）中的实验表明，与用于稠密线性代数（DLA）的优化软件包中的基于经典HT的QR因式分解实现相比，MHT能够实现稍好或相等的性能。我们实现MHT的密集线性代数（DLA）的定制平台上，并显示MHT实现1.3倍的性能比本地实现的经典HT在同一加速器。对于基于QR分解的HT和MHT的自定义实现，我们还确定了在可重构数据路径（RDP）上实现的HT和MHT的DAG中的宏操作。我们还观察到，由于MHT中计算的重新安排，MHT的自定义实现能够在多核和GPGPU上实现比通用矩阵乘法（GEMM）在用于多核和GPGPU的高度调谐的DLA软件包上报告的性能改进高12%的性能改进，这是违反直觉的。
英文摘要：
We present efficient realization of Householder Transform (HT) based QR factorization through algorithm-architecture co-design where we achieve performance improvement of 3-90x in-terms of Gflops/watt over state-of-the-art multicore, General Purpose Graphics Processing Units (GPGPUs), Field Programmable Gate Arrays (FPGAs), and ClearSpeed CSX700. Theoretical and experimental analysis of classical HT is performed for opportunities to exhibit higher degree of parallelism where parallelism is quantified as a number of parallel operations per level in the Directed Acyclic Graph (DAG) of the transform. Based on theoretical analysis of classical HT, an opportunity re-arrange computations in the classical HT is identified that results in Modified HT (MHT) where it is shown that MHT exhibits 1.33x times higher parallelism than classical HT. Experiments in off-the-shelf multicore and General Purpose Graphics Processing Units (GPGPUs) for HT and MHT suggest that MHT is capable of achieving slightly better or equal performance compared to classical HT based QR factorization realizations in the optimized software packages for Dense Linear Algebra (DLA). We implement MHT on a customized platform for Dense Linear Algebra (DLA) and show that MHT achieves 1.3x better performance than native implementation of classical HT on the same accelerator. For custom realization of HT and MHT based QR factorization, we also identify macro operations in the DAGs of HT and MHT that are realized on a Reconfigurable Data-path (RDP). We also observe that due to re-arrangement in the computations in MHT, custom realization of MHT is capable of achieving 12% better performance improvement over multicore and GPGPUs than the performance improvement reported by General Matrix Multiplication (GEMM) over highly tuned DLA software packages for multicore and GPGPUs which is counter-intuitive.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
