Contemporary field-programmable gate arrays (FPGAs) are predestined for the application of finite impulse response (FIR) filters. Their embedded digital signal processing (DSP) blocks for multiply-accumulate operations enable efficient fixed-point computations, in cases where the filter structure is accurately mapped to the dedicated hardware architecture. This brief presents a generic systolic structure for high-order FIR filters, efficiently exploiting the hardware resources of an FPGA in terms of routability and timing. Although this seems to be an easily implementable task, the synthesizing tools require an adaptation of the straightforward digital filter implementation for an optimal mapping. Using the example of a symmetric FIR filter with 90 taps, we demonstrate the performance of the proposed structure with FPGAs from Xilinx and Altera. The implementation utilizes less than 1% of slice logic and runs at clock frequencies up to 526 MHz. Moreover, an enhancement of the structure ultimately provides an extended dynamic range for the quantized coefficients without the costs of additional slice logic.
Reconfigurable Hardware Implementation of the Successive Overrelaxation Method
在本章中，我们研究了在可重构硬件中实现SOR的可行性。我们使用Handel-C，一个更高层次的设计工具，编码我们的设计，这是分析，综合，并放置和路由使用FPGA的专有软件（DK设计套件，Xilinx ISE 8.1i，和Quartus II 5.1）。我们的目标是Virtex II Pro、Altera Stratix和Spartan 3L，后者嵌入在Celoxica基于FPGA的RC 10系统中。我们报告了针对Virtex II Pro的计时结果，并将其与用C++编写并在通用处理器（GPP）上运行的软件版本结果进行比较。
Stream Decoding with Confidence Scores at Room and Cryogenic Temperatures
Quantum Motion（量子运动）；Department of Materials, University of Oxford（牛津大学材料系）；Center for Quantum Information and Quantum Biology, The University of Osaka（大阪大学量子信息与量子生物学中心）
