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arXiv 1609.04567cs.DC
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一种用于迭代模板+ reduce的并行模式

A parallel pattern for iterative stencil + reduce

M. Aldinucci, M. Danelutto, M. Drocco, P. Kilpatrick, C. Misale, G. Peretti Pezzi, M. Torquati

摘要:

我们提倡使用Loop-of-Stencil-Reduce模式来简化异构多核平台上数据并行程序的实现。Loop-of-stencil-reduce足够通用,可以在数据并行和流应用程序中或两者的组合中使用map、reduce、map-reduce、stencil、stencil-reduce,以及更重要的是,它们在循环中的使用。该模式使得在不同的GPU上部署单个模板计算内核成为可能。我们讨论了在FastFlow中实现Loop-of-stencil-reduce,FastFlow是一个基于并行模式的应用程序实现框架。实验来说明使用环的模板减少在开发数据并行内核运行在异构系统上。

英文摘要:

We advocate the Loop-of-stencil-reduce pattern as a means of simplifying the implementation of data-parallel programs on heterogeneous multi-core platforms. Loop-of-stencil-reduce is general enough to subsume map, reduce, map-reduce, stencil, stencil-reduce, and, crucially, their usage in a loop in both data-parallel and streaming applications, or a combination of both. The pattern makes it possible to deploy a single stencil computation kernel on different GPUs. We discuss the implementation of Loop-of-stencil-reduce in FastFlow, a framework for the implementation of applications based on the parallel patterns. Experiments are presented to illustrate the use of Loop-of-stencil-reduce in developing data-parallel kernels running on heterogeneous systems.

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