DiaSys：通过片上诊断提高SoC洞察力
DiaSys: Improving SoC Insight Through On-Chip Diagnosis
摘要：
为了找到在多处理器片上系统（MPSoC）上运行的软件中的功能或非功能缺陷（bug）的原因，开发人员需要深入了解芯片。跟踪系统以高片外带宽要求为代价，非侵入性地提供这种洞察。这个I/O瓶颈限制了可观测性，随着更多的功能集成在片上，这个问题变得更加严重。在本文中，我们提出了DiaSys，MPSoC诊断系统的潜力，以取代今天的跟踪系统。其主要思想是在芯片上部分执行观测数据的分析;因此，更多的信息和更少的数据被发送到所连接的主机PC。使用DiaSys时，数据分析由诊断应用程序执行。它的输入是事件，这些事件是由观察硬件在程序执行中的感兴趣的点生成的（如函数调用）。它的输出是具有更高信息密度的事件。事件转换被建模为一个简单的应用程序。对于执行，它部分映射到专用和分布式片上组件，部分映射到主机PC;片外边界对诊断应用程序的开发人员是透明的。我们实现DiaSys作为扩展到现有的SoC与四个瓦片和一个网状网络上运行的FPGA平台。两个使用示例证实，DiaSys足够灵活，可以取代跟踪系统，同时显著降低片外带宽要求。在我们的例子中，调试一个竞争条件错误，并创建一个锁争用配置文件，我们看到跟踪带宽减少了三个数量级以上，与普通跟踪系统创建的完整跟踪相比。
英文摘要：
To find the cause of a functional or non-functional defect (bug) in software running on a multi-processor System-on-Chip (MPSoC), developers need insight into the chip. Tracing systems provide this insight non-intrusively, at the cost of high off-chip bandwidth requirements. This I/O bottleneck limits the observability, a problem becoming more severe as more functionality is integrated on-chip. In this paper, we present DiaSys, an MPSoC diagnosis system with the potential to replace today's tracing systems. Its main idea is to partially execute the analysis of observation data on the chip; in consequence, more information and less data is sent to the attached host PC. With DiaSys, the data analysis is performed by the diagnosis application. Its input are events, which are generated by observation hardware at interesting points in the program execution (like a function call). Its outputs are events with higher information density. The event transformation is modeled as dataflow application. For execution, it is mapped in part to dedicated and distributed on-chip components, and in part to the host PC; the off-chip boundary is transparent to the developer of the diagnosis application. We implement DiaSys as extension to an existing SoC with four tiles and a mesh network running on an FPGA platform. Two usage examples confirm that DiaSys is flexible enough to replace a tracing system, while significantly lowering the off-chip bandwidth requirements. In our examples, the debugging of a race-condition bug, and the creation of a lock contention profile, we see a reduction of trace bandwidth of more than three orders of magnitude, compared to a full trace created by a common tracing system.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
