RIPL：一种基于FPGA的高效图像处理器DSL
RIPL: An Efficient Image Processing DSL for FPGAs
摘要：
现场可编程门阵列（FPGA）可以通过利用图像操作中的细粒度并行机会来加速图像处理。FPGA语言设计通常是现有语言的子集或扩展，尽管这些语言通常缺乏合适的硬件计算模型，因此将其编译为FPGA会导致设计效率低下。此外，这些语言缺乏图像处理领域特异性。我们的解决方案是RIPL，一种用于FPGA的图像处理领域特定语言（DSL）。它有算法框架来表达图像处理，这些算法框架被用来生成高度并发和内存高效的图像处理组件的深层管道。
英文摘要：
Field programmable gate arrays (FPGAs) can accelerate image processing by exploiting fine-grained parallelism opportunities in image operations. FPGA language designs are often subsets or extensions of existing languages, though these typically lack suitable hardware computation models so compiling them to FPGAs leads to inefficient designs. Moreover, these languages lack image processing domain specificity. Our solution is RIPL, an image processing domain specific language (DSL) for FPGAs. It has algorithmic skeletons to express image processing, and these are exploited to generate deep pipelines of highly concurrent and memory-efficient image processing components.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
