雷达处理应用中GPU上的高效FFT映射：建模与实现
Efficient FFT mapping on GPU for radar processing application: modeling and implementation
摘要：
通用多处理器（在我们的例子中，英特尔IvyBridge和英特尔Haswell）越来越多地为以前的多核架构添加GPU计算能力。当用于具有密集信号处理要求的嵌入式应用（对我们来说，合成孔径雷达）时，它们必须不断计算卷积算法，例如著名的快速傅立叶变换。由于其“分形”性质（典型的蝴蝶形状，较大的FFT定义为较小FFT与辅助数据阵列转置函数的组合），人们可以希望分析计算可以在基本GPU计算块上本地执行的最大FFT的大小。然后，整个应用程序必须围绕这个给定的构建块大小进行组织。现在，由于CPU和GPU之间的各种内存级别之间的数据传输所涉及的现象，这种方案的最优性只能粗略预测（因为通信往往会及时克服计算的复杂性）。因此，这里需要（理论）分析方法和（实际）运行时验证的混合。正如我们将说明的，这发生在两个阶段，首先在决定给定的基本FFT块大小的级别，然后在完整的应用级别。
英文摘要：
General-purpose multiprocessors (as, in our case, Intel IvyBridge and Intel Haswell) increasingly add GPU computing power to the former multicore architectures. When used for embedded applications (for us, Synthetic aperture radar) with intensive signal processing requirements, they must constantly compute convolution algorithms, such as the famous Fast Fourier Transform. Due to its "fractal" nature (the typical butterfly shape, with larger FFTs defined as combination of smaller ones with auxiliary data array transpose functions), one can hope to compute analytically the size of the largest FFT that can be performed locally on an elementary GPU compute block. Then, the full application must be organized around this given building block size. Now, due to phenomena involved in the data transfers between various memory levels across CPUs and GPUs, the optimality of such a scheme is only loosely predictable (as communications tend to overcome in time the complexity of computations). Therefore a mix of (theoretical) analytic approach and (practical) runtime validation is here needed. As we shall illustrate, this occurs at both stage, first at the level of deciding on a given elementary FFT block size, then at the full application level.
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