arXiv 1502.074462015-02-26cs.CVcs.DCcs.PF

嵌入式多处理器上计算机视觉应用的潜在加速比估计

Estimating the Potential Speedup of Computer Vision Applications on Embedded Multiprocessors

Univ. Grenoble Alpes（格勒诺布尔阿尔卑斯大学）；CNRS（法国国家科学研究中心）；STMicroelectronincs（意法半导体）

Vítor Schwambach, Sébastien Cleyet-Merle, Alain Issard, Stéphane Mancini

备注：: Presented at DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS 2015) (arXiv:1502.07241)

摘要：

计算机视觉应用构成了嵌入式多核架构的关键驱动力之一。尽管新架构中可用内核的数量不断增加，但设计应用程序以最大限度地利用平台仍然是一项挑战。从这个意义上说，并行性能预测工具可以帮助开发人员了解应用程序的特性，并找到最合适的并行化策略。在这项工作中，我们提出了一种方法，早期并行性能估计嵌入式多处理器从顺序应用程序的痕迹。我们描述了它在Parana中的实现，Parana是一个快速跟踪驱动的模拟器，针对STMicroelectronics的STxP70专用多处理器（ASMP）上的OpenMP应用。FAST关键点检测器应用的结果显示，与参考循环近似模拟器相比，误差幅度小于10%，建模工作量更低，执行时间最多快20倍。

英文摘要：

Computer vision applications constitute one of the key drivers for embedded multicore architectures. Although the number of available cores is increasing in new architectures, designing an application to maximize the utilization of the platform is still a challenge. In this sense, parallel performance prediction tools can aid developers in understanding the characteristics of an application and finding the most adequate parallelization strategy. In this work, we present a method for early parallel performance estimation on embedded multiprocessors from sequential application traces. We describe its implementation in Parana, a fast trace-driven simulator targeting OpenMP applications on the STMicroelectronics' STxP70 Application-Specific Multiprocessor (ASMP). Results for the FAST key point detector application show an error margin of less than 10% compared to the reference cycle-approximate simulator, with lower modeling effort and up to 20x faster execution time.

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