COTS多核系统内存干扰延迟分析
Parallelism-Aware Memory Interference Delay Analysis for COTS Multicore Systems
摘要：
在现代商用现货（COTS）多核系统中，每个核可以一次生成许多并行存储器请求。在DRAM控制器中对这些并行请求的处理极大地影响了在平台上运行任务所经历的存储器干扰延迟。在本文中，我们建立了一个现代的COTS多核系统，它有一个非阻塞的最后一级缓存（LLC）和DRAM控制器，优先读写。为了尽量减少干扰，我们专注于LLC和DRAM银行分区系统。基于该模型，我们提出了一种分析，计算最坏情况下的内存干扰延迟的安全上限。我们在一个真正的COTS多核平台上使用一组精心设计的综合基准测试和SPEC2006基准测试验证了我们的分析。评估结果表明，我们的分析是更准确地捕捉最坏情况下的内存干扰延迟，并提供更安全的上限相比，最近提出的分析，显着低估的延迟。
英文摘要：
In modern Commercial Off-The-Shelf (COTS) multicore systems, each core can generate many parallel memory requests at a time. The processing of these parallel requests in the DRAM controller greatly affects the memory interference delay experienced by running tasks on the platform. In this paper, we model a modern COTS multicore system which has a nonblocking last-level cache (LLC) and a DRAM controller that prioritizes reads over writes. To minimize interference, we focus on LLC and DRAM bank partitioned systems. Based on the model, we propose an analysis that computes a safe upper bound for the worst-case memory interference delay. We validated our analysis on a real COTS multicore platform with a set of carefully designed synthetic benchmarks as well as SPEC2006 benchmarks. Evaluation results show that our analysis is more accurately capture the worst-case memory interference delay and provides safer upper bounds compared to a recently proposed analysis which significantly under-estimate the delay.
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