基于动态可重构收发器IP核的高速XAUI设计
Design of a High Speed XAUI Based on Dynamic Reconfigurable Transceiver IP Core
摘要：
将动态可重构收发器应用于高速接口设计中，可以方便地解决保证信号完整性、降低误码率等关键技术问题。在本文中，我们设计了一个高速XAUI（10Gbps以太网附件单元接口），透明地扩展XGMII的物理范围。重点研究了以下几个方面：（1）知识产权核心使用。Altera公司在Quartus II MegaWizard插件管理器中提供了两个用于XAUI设计的收发器IP核，即ALTGX_RECO？FIG实例和ALTGX实例，我们可以通过改变设备的设置来获得各种组，而无需关闭电源。这两个模块可以完成PCS（物理编码子层）和PMA（物理介质附着）的功能，但是具有更高的效率和可靠性。(2)1+1保护。在设计中，采用了两个并行工作的ALTGX IP核，分别命名为XAUI0和XAUI1。前者作为主通道，后者作为冗余通道。当XAUI0由于某些原因停止服务时，XAUI1将开始工作以保持业务。(3)RTL（寄存器传输级）的Verilog HDL编码和仿真.创建ALTGX_RECO？FIG实例和ALTGX实例，在ALTGXB Megafunction中启用动态重配置，然后连接ALTGX_RECO？图与ALTGX实例。在RTL级编码后，在FPGA仿真器上进行了仿真。验证结果表明，数据包传输效率高。FPGA使高速光通信系统的设计得以简化。
英文摘要：
By using the dynamic reconfigurable transceiver in high speed interface design, designer can solve critical technology problems such as ensuring signal integrity conveniently, with lower error binary rate. In this paper, we designed a high speed XAUI (10Gbps Ethernet Attachment Unit Interface) to transparently extend the physical reach of the XGMII. The following points are focused: (1) IP (Intellectual Property) core usage. Altera Co. offers two transceiver IP cores in Quartus II MegaWizard Plug-In Manager for XAUI design which is featured of dynamic reconfiguration performance, that is, ALTGX_RECO?FIG instance and ALTGX instance, we can get various groups by changing settings of the devices without power off. These two blocks can accomplish function of PCS (Physical Coding Sub-layer) and PMA (Physical Medium Attachment), however, with higher efficiency and reliability. (2) 1+1 protection. In our design, two ALTGX IP cores are used to work in parallel, which named XAUI0 and XAUI1. The former works as the main channel while the latter redundant channel. When XAUI0 is out of service for some reasons, XAUI1 will start to work to keep the business. (3) RTL (Register Transfer Level) coding with Verilog HDL and simulation. Create the ALTGX_RECO?FIG instance and ALTGX instance, enable dynamic reconfiguration in the ALTGXB Megafunction, then connect the ALTGX_RECO?FIG with the ALTGX instances. After RTL coding, the design was simulated on VCS simulator. The validated result indicates that the packets are transferred efficiently. FPGA makes high-speed optical communication system design simplified.
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