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arXiv 1301.4490cs.DC
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Regional Consistency:非缓存一致性系统的可编程性和性能

Regional Consistency: Programmability and Performance for Non-Cache-Coherent Systems

Bharath Ramesh, Calvin J. Ribbens, Srinidhi Varadarajan

摘要:

并行程序员面临着可编程性和性能这两个经常不可调和的目标。HPC系统使用分布式存储器来实现可扩展性,从而牺牲了共享存储器编程模型的可编程性优势。此外,异构体系结构的快速采用(通常具有非高速缓存一致性存储器系统)进一步增加了支持共享存储器编程模型的挑战。我们的主要目标是定义一个内存一致性模型,提出了熟悉的基于线程的共享内存编程模型,但允许良好的应用程序性能的非缓存一致性系统,包括分布式内存集群和基于加速器的系统。我们提出了区域一致性(RegC),一个新的一致性模型,实现这一目标。在多达256个处理器的代表性基准测试的结果表明,在我们的原型分布式共享内存系统的背景下,RegC的潜力。

英文摘要:

Parallel programmers face the often irreconcilable goals of programmability and performance. HPC systems use distributed memory for scalability, thereby sacrificing the programmability advantages of shared memory programming models. Furthermore, the rapid adoption of heterogeneous architectures, often with non-cache-coherent memory systems, has further increased the challenge of supporting shared memory programming models. Our primary objective is to define a memory consistency model that presents the familiar thread-based shared memory programming model, but allows good application performance on non-cache-coherent systems, including distributed memory clusters and accelerator-based systems. We propose regional consistency (RegC), a new consistency model that achieves this objective. Results on up to 256 processors for representative benchmarks demonstrate the potential of RegC in the context of our prototype distributed shared memory system.

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