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arXiv 1301.2013quant-phcs.CR
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基于FPGA的QKD系统快速误差校正实时设计

A real-time design based on FPGA for Expeditious Error Reconciliation in QKD system

Ke Cui, Jian Wang, Hong-fei Zhang, Chun-li Luo, Ge Jin, Teng-yun Chen

摘要:

在高速量子密钥分发系统中,差错协调往往是影响系统性能的瓶颈。通过公共信道交换公共信息,可以在通信双方生成相同的密钥。然而,出于安全原因消除所公开的比特的必要性降低了最终的密钥速率。为了提高该密钥速率,应当最小化所公开的比特的量。此外,减少花在错误协调上的时间也提高了密钥速率。本文介绍了一种在现场可编程门阵列中实现离散变量量子密钥分发系统的快速误差校正的实用方法,并举例说明了这种方法相对于在PC机上运行的其它类似算法的优越性。实验结果证明了该协议的快速性。

英文摘要:

For high-speed quantum key distribution systems, error reconciliation is often the bottleneck affecting system performance. By exchanging common information through a public channel, the identical key can be generated on both communicating sides. However, the necessity to eliminate disclosed bits for security reasons lowers the final key rate. To improve this key rate, the amount of disclosed bits should be minimized. In addition, decreasing the time spent on error reconciliation also improves the key rate. In this paper we introduce a practical method for expeditious error reconciliation implemented in a Field Programmable Gate Array for a discrete variable quantum key distribution system, and illustrate the superiority of this method to other similar algorithms running on a PC. Experimental results demonstrate the rapidity of the proposed protocol.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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