基于粒子群算法的VLSI电路低功耗测试
Particle Swarm Optimization Framework for Low Power Testing of VLSI Circuits
摘要：
时序电路中的功耗是由于被测电路的切换计数增加而引起的，这取决于所应用的测试向量。如果连续的测试向量序列具有更多的触发性质，则触发器的触发率肯定更高。触发器的切换越高，功耗越大。为了克服这个问题，一种方法是使用遗传算法在短时间内获得高故障覆盖率的测试向量，然后对测试向量进行汉明距离管理。这种方法很耗时，需要更多的努力。另一种方法，这是本文的目的是基于粒子群算法的框架来优化功耗。这里的目标是将整个测试向量设置在时间段“T”的帧中，使得该帧由不仅提供高故障覆盖率而且还将向量布置在帧中以产生最小切换的所有那些向量串组成。
英文摘要：
Power dissipation in sequential circuits is due to increased toggling count of Circuit under Test, which depends upon test vectors applied. If successive test vectors sequences have more toggling nature then it is sure that toggling rate of flip flops is higher. Higher toggling for flip flops results more power dissipation. To overcome this problem, one method is to use GA to have test vectors of high fault coverage in short interval, followed by Hamming distance management on test patterns. This approach is time consuming and needs more efforts. Another method which is purposed in this paper is a PSO based Frame Work to optimize power dissipation. Here target is to set the entire test vector in a frame for time period 'T', so that the frame consists of all those vectors strings which not only provide high fault coverage but also arrange vectors in frame to produce minimum toggling.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
