基于片上网络的FPGA高性能混合两层路由器结构
High Performance Hybrid Two Layer Router Architecture for FPGAs Using Network On Chip
摘要：
片上网络是最近采用的一种解决方案范例，用于提高多核设计的性能。其关键思想是以网络方式互连各种计算模块（IP核），并在它们之间同时传输数据包，从而提高性能。除了通过使多个分组处于飞行中来提高性能之外，NoC还呈现出许多其他优点，包括可扩展性、功率效率和通过模块化设计的组件重用。这项工作的重点是设计和开发的高性能通信架构的FPGA使用NoCs一旦完全开发，上述方法可以用来增强目前的FPGA设计流程，实现多核SoC应用。本文设计并实现了一个基于FPGA的片上网络架构--可重构系统多时钟片上网络（MultiClock OnChip Network for Reconfigurable Systems，MoCReS）。我们提出了一种新的微体系结构的混合两层路由器，支持两个包交换通信，在其本地和定向端口，以及，在直接连接到它的多个IP核之间进行时分复用电路交换通信。高级路由器架构的布局和路由VHDL模型的结果显示，NoC带宽平均提高了20.4（与传统NoC相比，最大值为24%）。我们参数化的混合路由器模型的端口数，通道宽度和bRAM深度，并开发一个网络组件库（MoClib库）。为了在会议论文集上发表你的论文，你必须将本文档作为一个指令集和一个模板，你可以在其中键入自己的文本。如果你的论文不符合要求的格式，你会被要求修改它。
英文摘要：
Networks on Chip is a recent solution paradigm adopted to increase the performance of Multicore designs. The key idea is to interconnect various computation modules (IP cores) in a network fashion and transport packets simultaneously across them, thereby gaining performance. In addition to improving performance by having multiple packets in flight, NoCs also present a host of other advantages including scalability, power efficiency, and component reuse through modular design. This work focuses on design and development of high performance communication architectures for FPGAs using NoCs Once completely developed, the above methodology could be used to augment the current FPGA design flow for implementing multicore SoC applications. We design and implement an NoC framework for FPGAs, MultiClock OnChip Network for Reconfigurable Systems (MoCReS). We propose a novel microarchitecture for a hybrid two layer router that supports both packetswitched communications, across its local and directional ports, as well as, time multiplexed circuitswitched communications among the multiple IP cores directly connected to it. Results from place and route VHDL models of the advanced router architecture show an average improvement of 20.4 percent in NoC bandwidth (maximum of 24 percent compared to a traditional NoC). We parameterize the hybrid router model over the number of ports, channel width and bRAM depth and develop a library of network components (MoClib Library). For your paper to be published in the conference proceedings, you must use this document as both an instruction set and as a template into which you can type your own text. If your paper does not conform to the required format, you will be asked to fix it.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
