PANDA在线计算计划
Plans for PANDA Online Computing
摘要:
PANDA实验将不使用任何硬件触发器,即所有原始数据都以约280 GB/s的带宽在数据采集中流式传输。PANDA在线系统旨在通过在FPGA(现场可编程门阵列)上使用VHDL(超高速集成电路硬件描述语言)编程的重建算法执行约800倍的数据缩减。
英文摘要:
The PANDA experiment will not use any hardware trigger, i.e. all raw data are streaming in the data acquisition with a bandwidth of ~280 GB/s. The PANDA Online System is designed to perform data reduction by a factor of ~800 by reconstruction algorithms programmed in VHDL (Very High Speed Integrated Circuit Hardware Description Language) on FPGAs (Field Programmable Gate Arrays).
机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。