介绍一种带宽受限环路内核的性能模型
Introducing a Performance Model for Bandwidth-Limited Loop Kernels
摘要：
我们提出了一个性能模型的带宽有限的循环内核，这是建立在现代高速缓存为基础的微架构的分析。该模型允许对现有指令码进行准确的性能预测和评估。它提供了对不同存储层次结构级别的性能是如何构成的深入理解。原始内存加载，存储和复制操作和流矢量三元组的性能进行了分析，并在三个现代x86型四核架构基准，以证明该模型的能力。
英文摘要：
We present a performance model for bandwidth limited loop kernels which is founded on the analysis of modern cache based microarchitectures. This model allows an accurate performance prediction and evaluation for existing instruction codes. It provides an in-depth understanding of how performance for different memory hierarchy levels is made up. The performance of raw memory load, store and copy operations and a stream vector triad are analyzed and benchmarked on three modern x86-type quad-core architectures in order to demonstrate the capabilities of the model.
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