基于CRT的长BCH编码高速并行结构
CRT-Based High Speed Parallel Architecture for Long BCH Encoding
摘要：
BCH（Bose-Chaudhuri-Hocquenghen）纠错码（[1]-[2]）在通信系统和数字技术中得到了广泛的应用。基于线性反馈移位寄存器（LFSR）的长BCH码直接编码存在串行输入和串行输出限制以及某些“异”门的大扇出效应。这使得基于LFSR的长BCH码编码器在某些应用中无法跟上数据传输速度。文献[3]-[8]提出了几种长循环码的并行长并行编码器。文献[7]和[8]提出了用J-展开方法和一些代数处理来消除大扇出效应的技术。本文提出了一种基于中国剩余定理的长BCH编码并行结构。我们的新技术可以用来消除扇出瓶颈。对我们基于CRT的架构的长BCH编码的速度的唯一限制是$log_2N$，其中$N$是BCH码的长度。
英文摘要：
BCH (Bose-Chaudhuri-Hocquenghen) error correcting codes ([1]-[2]) are now widely used in communication systems and digital technology. Direct LFSR(linear feedback shifted register)-based encoding of a long BCH code suffers from serial-in and serial-out limitation and large fanout effect of some XOR gates. This makes the LFSR-based encoders of long BCH codes cannot keep up with the data transmission speed in some applications. Several parallel long parallel encoders for long cyclic codes have been proposed in [3]-[8]. The technique for eliminating the large fanout effect by J-unfolding method and some algebraic manipulation was presented in [7] and [8] . In this paper we propose a CRT(Chinese Remainder Theorem)-based parallel architecture for long BCH encoding. Our novel technique can be used to eliminate the fanout bottleneck. The only restriction on the speed of long BCH encoding of our CRT-based architecture is $log_2N$, where $N$ is the length of the BCH code.
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