使用单面掩模对准器的图案化背栅：应用于密度匹配的电子-空穴双层膜
Patterned backgating using single-sided mask aligners: application to density-matched electron-hole bilayers
摘要：
我们报告了我们的工作，在薄的（50-60 $μ$ m）\Roman{roman3} - \Roman{roman5}半导体样品上制造光刻对准图案化的背栅，仅使用{ \it单面掩模对准器}。与此同时，我们还提出了一种方法，使用廉价的红外发光二极管（LED）和廉价的（消费）数码相机拍摄薄图案化芯片的两侧。描述了一种使用超声波结合器接触样品两侧的稳健方法。此外，我们提出了一个数学模型来分析通过掺杂层和异质结，通常存在于大多数GaAs基器件的电化学电位的变化。我们利用该技术和模型的估计来制造电子-空穴双层器件，其中每个层都是单独接触的并且具有可调的密度。电子层和空穴层由25或15 nm宽的势垒分开。在这两种情况下，可以通过使用适当的偏置电压来匹配密度。
英文摘要：
We report our work on fabricating lithographically aligned patterned backgates on thin (50-60$μ$m) \Roman{roman3}-\Roman{roman5} semiconductor samples using {\it single sided mask aligners only}. Along with this we also present a way to photograph both sides of a thin patterned chip using inexpensive infra-red light emitting diodes (LED) and an inexpensive (consumer) digital camera. A robust method of contacting both sides of a sample using an ultrasonic bonder is described. In addition we present a mathematical model to analyse the variation of the electrochemical potential through the doped layers and heterojunctions that are normally present in most GaAs based devices. We utilise the technique and the estimates from our model to fabricate an electron-hole bilayer device in which each layer is separately contacted and has tunable densities. The electron and hole layers are separated by barriers either 25 or 15nm wide. In both cases, the densities can be matched by using appropriate bias voltages.
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