具有多个内存控制器的高线程多核CPU的数据访问优化
Data access optimizations for highly threaded multi-core CPUs with multiple memory controllers
摘要：
具有多个内存控制器的处理器和系统架构在具有常规访问模式的代码上容易显示出瓶颈和不稳定的性能数字。虽然这种影响以高速缓存抖动和别名冲突的形式为人们所熟知，但当涉及内存访问时，它们会变得更加严重。使用新的Sun UltraCore T2处理器作为原型多核设计，我们分析了低级别和应用程序基准测试中的性能模式，并通过仔细的数据布局和填充展示了规避瓶颈的方法。
英文摘要：
Processor and system architectures that feature multiple memory controllers are prone to show bottlenecks and erratic performance numbers on codes with regular access patterns. Although such effects are well known in the form of cache thrashing and aliasing conflicts, they become more severe when memory access is involved. Using the new Sun UltraSPARC T2 processor as a prototypical multi-core design, we analyze performance patterns in low-level and application benchmarks and show ways to circumvent bottlenecks by careful data layout and padding.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
