可逆BCD算法的部分可逆门（PRG）
Partial Reversible Gates(PRG) for Reversible BCD Arithmetic
摘要：
IEEE 754r是IEEE 754浮点标准的持续修订版，该标准的主要增强是增加了十进制格式。此外，近年来可逆逻辑已经成为一种有前途的计算范例，其在低功耗CMOS、量子计算、纳米技术和光计算中具有应用。可逆逻辑的主要目标是最小化可逆门和垃圾输出的数量。因此，本文提出了新的概念，部分可逆门，将满足可逆性标准的特定情况下，在BCD算术。在设计可逆BCD算术电路时，提出了部分可逆门的概念，以减少可逆门的数目和无用输出。
英文摘要：
IEEE 754r is the ongoing revision to the IEEE 754 floating point standard and a major enhancement to the standard is the addition of decimal format. Furthermore, in the recent years reversible logic has emerged as a promising computing paradigm having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. The major goal in reversible logic is to minimize the number of reversible gates and garbage outputs. Thus, this paper proposes the novel concept of partial reversible gates that will satisfy the reversibility criteria for specific cases in BCD arithmetic. The partial reversible gate is proposed to minimize the number of reversible gates and garbage outputs, while designing the reversible BCD arithmetic circuits.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
