事务级软硬件协同仿真中减少信道流量的预测打包方案
A Prediction Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation
摘要：
本文提出了一种有效的模拟器和加速器之间的通道使用的方案，其中加速器模型的一些RTL子块在基于加速器的硬件/软件协同仿真，而模拟器运行的事务级模型的整个芯片的其余部分被验证。对于传统的仿真加速器，仿真器和加速器的评估在每个有效的仿真时间交替进行，这导致由于仿真器-加速器通道访问的启动开销而导致的较差的仿真性能。通过将通道上的多个事务合并为单个突发流量，可以减少启动开销。我们提出了一个预测打包方案，通过合并尽可能多的事务到一个突发流量的基础上，预测和回滚减少信道流量。在理想条件下，预测精度为100%，与传统方法相比，所提出的方法显示出1500%的性能增益。
英文摘要：
This paper presents a scheme for efficient channel usage between simulator and accelerator where the accelerator models some RTL sub-blocks in the accelerator-based hardware/software co-simulation while the simulator runs transaction-level model of the remaining part of the whole chip being verified. With conventional simulation accelerator, evaluations of simulator and accelerator alternate at every valid simulation time, which results in poor simulation performance due to startup overhead of simulator-accelerator channel access. The startup overhead can be reduced by merging multiple transactions on the channel into a single burst traffic. We propose a predictive packetizing scheme for reducing channel traffic by merging as many transactions into a burst traffic as possible based on 'prediction and rollback.' Under ideal condition with 100% prediction accuracy, the proposed method shows a performance gain of 1500% compared to the conventional one.
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