面向系统芯片优化多点测试的片上测试架构设计
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips
摘要：
多站点测试是提高测试吞吐量和降低测试成本的一种流行而有效的方法。我们提出了一个测试吞吐量模型，在该模型中，我们专注于晶圆测试，并考虑参数，如测试时间，索引时间，失败后中止，和接触良率。传统的多站点测试需要足够的ATE资源，例如ATE通道，以允许并行测试多个SOC。在本文中，我们设计和优化片上DfT，以最大限度地提高测试吞吐量为一个给定的SOC和ATE。片上DfT由E-RPCT包装器组成，对于模块化SOC，还包括模块包装器和TAM。我们目前的实验结果为飞利浦SOC和几个ITC'02 SOC测试基准。
英文摘要：
Multi-site testing is a popular and effective way to increase test throughput and reduce test costs. We present a test throughput model, in which we focus on wafer testing, and consider parameters like test time, index time, abort-on-fail, and contact yield. Conventional multi-site testing requires sufficient ATE resources, such as ATE channels, to allow to test multiple SOCs in parallel. In this paper, we design and optimize on-chip DfT, in order to maximize the test throughput for a given SOC and ATE. The on-chip DfT consists of an E-RPCT wrapper, and, for modular SOCs, module wrappers and TAMs. We present experimental results for a Philips SOC and several ITC'02 SOC Test Benchmarks.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
