SoCs快速成型仿真加速的循环精确二进制翻译
Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs
摘要：
在本文中，应用周期准确的二进制翻译器的快速原型的SoC。这个翻译器生成的代码运行在一个快速原型系统组成的VLIW处理器和FPGA。所生成的代码被注释有与所转换的程序的执行并行地触发硬件的周期生成的信息。VLIW处理器执行转换后的程序，而FPGA包含用于并行周期生成的硬件和将VLIW处理器的总线适配到仿真处理器核的SoC总线的总线接口。
英文摘要：
In this paper, the application of a cycle accurate binary translator for rapid prototyping of SoCs will be presented. This translator generates code to run on a rapid prototyping system consisting of a VLIW processor and FPGAs. The generated code is annotated with information that triggers cycle generation for the hardware in parallel to the execution of the translated program. The VLIW processor executes the translated program whereas the FPGAs contain the hardware for the parallel cycle generation and the bus interface that adapts the bus of the VLIW processor to the SoC bus of the emulated processor core.
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