AI中文摘要
我们提出SPICE-Q,一个受SPICE启发的超导量子处理器设计-技术协同优化框架。SPICE-Q并非要取代HFSS、Qiskit Metal、pyEPR、SQcircuit、SQuADDS、scqubits或QuTiP等工具,而是旨在通过一条统一的、可追溯的数据链将它们连接起来,该数据链涵盖工艺规则、版图、电磁仿真、能量参与比与电路量化、哈密顿量提取、噪声分析、低温测试和制造反馈。核心映射是从工艺和PDK约束到版图几何、电磁模式、等效电路参数、有效哈密顿量,最终到频率、耦合、非谐性、退相干、读出性能和良率等指标。该流程必须捕获约瑟夫森结变异性、transmon频率分配、谐振器和Purcell约束、耦合器串扰、微波布线、3D互连、材料/界面损耗、封装模式和晶圆级工艺统计。通过引入标准化模型接口、统计参数模型、模型卡、版本治理以及来自低温和制造数据的闭环校准,SPICE-Q将超导量子芯片设计构建为一个工程工作流,而非孤立仿真的集合。我们认为,可扩展且容错的量子处理器将需要这样一个从器件物理和电磁场到量子动力学、噪声、可制造性和系统级良率的连续模型链。
英文摘要
We propose SPICE-Q, a SPICE-inspired design-technology co-optimization framework for superconducting quantum processors. Rather than replacing tools such as HFSS, Qiskit Metal, pyEPR, SQcircuit, SQuADDS, scqubits, or QuTiP, SPICE-Q aims to connect them through a unified, traceable data chain spanning process rules, layout, electromagnetic simulation, energy-participation-ratio and circuit quantization, Hamiltonian extraction, noise analysis, cryogenic test, and manufacturing feedback. The central mapping is from process and PDK constraints to layout geometry, electromagnetic modes, equivalent circuit parameters, effective Hamiltonians, and finally metrics such as frequency, coupling, anharmonicity, decoherence, readout performance, and yield. This flow must capture Josephson-junction variability, transmon frequency allocation, resonator and Purcell constraints, coupler crosstalk, microwave routing, 3D interconnects, material/interface loss, package modes, and wafer-scale process statistics. By introducing standardized model interfaces, statistical parameter models, model cards, version governance, and closed-loop calibration from cryogenic and fabrication data, SPICE-Q frames superconducting quantum-chip design as an engineering workflow rather than a collection of isolated simulations. We argue that scalable and fault-tolerant quantum processors will require such a continuous model chain from device physics and electromagnetic fields to quantum dynamics, noise, manufacturability, and system-level yield.